The present invention is related to memory systems and in particular to redundant memory systems for mitigating the effect of single event upset (SEU).
Memory systems oftentimes employ an error detection and correction (EDAC) circuit to ensure that data read from memory circuitry is correct. That is, the EDAC detects the presence of errors in the data received from the memory system and to the extent possible acts to correct the detected errors.
In aerospace applications, this problem is of particular importance. Memory devices used in aerospace applications are subject to high-energy neutrons and/or other particles that have the ability to flip or change the state of a particular memory cell in what is a called a ‘single-event upset’. In the past, risks associated with SEU events were avoided by using ‘hardened’ memory devices resistant to these particles. Past solutions include ‘hardening’ of the memory devices such that they are less susceptible to SEU events. However, ‘hardened’ memory devices are typically much more expensive than traditional memory devices. It would therefore be beneficial if traditional memory devices could be employed while still providing the required protection from SEU events.